The present invention relates to a semiconductor wafer with a notch cut in the periphery, and a method and an apparatus for chamfering the notch. A semiconductor wafer used as the substrate for semiconductor device such as semiconductor integrated circuit is commonly made in the following manner: a monocrystal rod (ingot) of silicon, for example, is sliced in the direction normal to the axis of the rod and then each round slice is subjected to lapping, etching, polishing, and other finishing treatments as the need arises. It is a normal practice to provide an orientation flat at a portion of the periphery of the wafer for the purpose of allowing one to know at a glance the direction of crystal orientation as well as facilitating the positioning of optical pattern. Since the orientation flat is provided by cutting away an arch portion from the periphery of the water, the cut away piece is sacrificed so that the number of effective chips obtained from a wafer is less than it would otherwise be.
In order to avoid the sacrificial cutting away of the wafer, it was proposed (e.g. in Japanese patent application No. 62-239517) to provide a small notch (commonly V-shaped or U-shaped) in the periphery of the semiconductor wafer in a manner such that the notch is effective of providing a guide for positioning of the optical pattern as well as of indicating the direction of crystal orientation.
Monocrystal silicon, GGG, and lithium tantalate, and the like of which semiconductor wafers are often made, are very hard and brittle and easy to break in the direction of crystal orientation. In these days, the processes for manufacturing wafers and those for manufacturing devices are mostly automatized, and in these automatized processes the wafers are shifted along the process lines incessantly with some possibility of collision and receiving physical shocks so that unless the peripheral edges of the wafers are chamfered the edges of the wafers are chipped, and the infinitesimal chips dropping from the wafers are responsible together with dust in the air for lowering of the properties of the device and hence to increasing in number of off-specification devices produced. Therefore, it has been conveniently practiced to chamfer the periphery of semiconductor wafer including the portion where orientation flat is formed.
However, in the case of the semiconductor wafers provided with a notch in the periphery, chamfering was not applied to the notch portion of the periphery, so that when the notch is brought in engagement with a positioning pin in a device manufacturing process, the likelihood is that the unchamfered notch is chipped and gives away infinitesimal chips to give rise to the problems described above.